1. Field of the Invention
The invention relates to a memory system for use in digital computers.
2. Prior Art
Countless memory systems are known for permitting a processing means (e.g., central processing unit, arithmetic logic unit, etc.) to select locations in a random-access memory (RAM). For purposes of discussion, and recognizing the pitfalls in characterizing memory systems, the prior art is briefly discussed in two general categories. One category (non-virtual memories) receives a logical address and employs some means such as an address extender technique, memory management unit (MMU), bank switching, etc., to provide a larger, physical address for addressing a RAM. In the second category, a larger logical address from the processing means is translated to a generally smaller, physical address for accessing the RAM. As will be seen, the present invention is more like the second category of memory systems than the first.
The first category of memory systems is typically used by microprocessors, and the like, and often uses an MMU. This unit receives a portion of the logical address and provides a portion of the physical address. For the mapping provided with this non-virtual storage, a physical address exists for each logical address.
In the second category, often two memories for storing data are employed. One, commonly referred to as a data cache, is a smaller, higher speed RAM (e.g., employing static devices and having a system cycle time of approximately 200 nsec.). Data frequently addressed by the processing means is stored in the data cache memory. A larger RAM (e.g., dynamic devices with system cycle times of 1-2 micro sec.) provides the bulk of the RAM storage. In a typical process, usually more than 90% of the time, data sought by the processing means is in the data cache and if not there, much greater than 99% of the time the data is in the dynamic RAM. A fast memory (address translation unit (ATU) or translation look-aside buffer) is used to examine addresses from the processing means and for providing addresses for the RAMs. As many as three serial accesses can be required with this arrangement. The effective cycle time for this memory system is in the 300-400 nsec. range for the described examples. The effective cycle time is reduced from what would appear to be faster access in the data cache, since to resolve a miss in the data cache, and actually access the main RAM requires approximately 1-2 microsec. because of the serial accessing. With the above described memory, for each context switch, the ATU cache must be reprogrammed, thus further reducing the speed of the memory system where context switching is required.
As will be seen, the present invention employs only one type of memory for data storage (e.g., dynamic RAMs) without the equivalent of a data cache. An associative memory operation used to identify locations in RAM occurs in parallel with the accessing of portions of the RAM to accelerate the overall cycle time. Context switching can occur much more quickly than with prior art systems. The cycle time in the invented system is slightly slower than in the above-described virtual memory systems. However, because of numerous operation advantages the effective cycle time in many cases is faster without the complications inherent in prior art memory systems. For instance, the invented system has a guaranteed, constant cycle time (assuming the data is in memory). This is particularly important for "pinned" or "locked" pages.